PPC64 VSX load/store instructions in stubs

[Gustavo Romero]

> Hi Martin
> 
> Thank you for reviewing the webrev.
> 
>> We could use a static variable for the default dscr value. It could be modified in VM_Version::config_dscr() and used by your restore code (load_const_optimized(tmp1, ...) instead of li(tmp1, 0)).
> 
> Absolutely, resetting DSCR to the default value (zero) is not right.
> 
> I did as you suggested and created a static variable modified and
> initialized from VM_Version::config_dscr(). Then I used it to get the
> current value of DSCR, set only the pre-fetch as deepest, and restore
> its previous value.
> 
> 
>> - The PPC-elf64abi-1.9 says: "Functions must ensure that the appropriate bits in the vrsave register are set for any vector registers they use. ...". I think not touching vrsave is the right thing for AIX and ppc64le, but I think we will either have to skip the optimization on ppc64 big endian or handle vrsave. Do you agree?
> 
> About the VRSAVE register, you are right, but there is a confusing here
> and it's my fault: I'm not using the VMX registers.
> 
> In my code I've used the VSX load/store instructions with a
> VectorRegister type, i.e. VR0 and VR1. It's OK if we look at the
> assembled instructions because, in the end, VR0 and VR1 will be
> converted to target (or source) registers number 0 and 1. But it's VSX
> registers 0 and 1 (VSR0 and VSR1) and not VMX (aka Altivec) registers
> 0 and 1 (VR0 and VR1).
> 
> There is indeed a relationship between VSR and VR registers, as
> we can see in the following diagram adapted from [1]:
> 
>        .---------------------------------.
> VSR( 0)|     FPR(0)     |                |
> VSR( 1)|     FPR(1)     |                |
>   ...  |      ...       |                |
>   ...  |      ...       |                |
> VSR(30)|     FPR(30)    |                |
> VSR(31)|     FPR(31)    |                |
> VSR(32)|              VR(0)              |
> VSR(33)|              VR(1)              |
>   ...  |               ...               |
>   ...  |               ...               |
> VSR(62)|              VR(30)             |
> VSR(63)|              VR(31)             |
>        '---------------------------------'
>         0                             127
> 
> However VMX registers VR0-31 are mapped to VSX VSR32-63 registers,
> and so we can use VSR0 and VSR1 (although they are also mapped to FPR,
> FPR0-13 are volatile). Thus actually in my code I was using VSR0 and
> VSR1 and not VR0 and VR1. Thus as VRSAVE only corresponds to
> VMX/Altivec registers (VR0-VR31), there is not need to take care of
> VRSAVE. I fixed the registers names/types in this new webrev.
> 
> I noted that the VSR registers were not implemented and thus I
> implemented them. Now VSX load/store instruction use VectorSRegister
> type. I'm using VSR0 and VSR1 registers in the stub, respecting the
> ABI.
> 
> Webrev:
> http://81.de.7a9f.ip4.static.sl-reverse.com./8154156/9/v2/
> 
> Best regards,
> Gustavo
> 
> [1] Power Architecture 64-Bit ELF V2 ABI https://goo.gl/LLXRwN, p. 43-44
> 

Hi Martin

The previous change was not restoring the DSCR value.

Here is the webwev with the fix included:
http://81.de.7a9f.ip4.static.sl-reverse.com./8154156/9/v3/

Thank you!

Best regards,
Gustavo