[PATCH v2] JDK-8222090: Add Hygon Dhyana support
Jinke Fan
fanjinke51 at yeah.net
Tue Apr 9 03:17:56 UTC 2019
Hi David,
This patch is used to support Hygon Dhyana x86 vendor id (HygonGenuine).
As Hygon Dhyana CPU share most architecture feature same as AMD Family 17h,
the patch adds Hygon CPU Vendor ID check to reuse AMD code paths.
The changes in patch v2 from David's comments,
add changes in:
- VM_Version_Ext::cpu_family_description(void)
- VM_Version_Ext::cpu_type_description(char* const buf, size_t buf_len)
Background:
Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture
between AMD and Haiguang Information Technology Co.,Ltd., aims at
providing high performance x86 processor for China server market.
Its first generation processor codename is Dhyana, which
originates from AMD technology and shares most of the
architecture with AMD's family 17h, but with different CPU Vendor
ID("HygonGenuine")/Family series number(Family 18h).
The patch is based on the original repository:
hg.openjdk.java.net/jdk/jdk
changeset: 54384:cd3b7ad53265
tag: tip
user: kvn
date: Tue Apr 02 09:45:52 2019 -0700
summary: 8221782: [Graal] Module jdk.internal.vm.compiler.management
has not been granted accessClassInPackage.jdk.vm.ci.services
Please help me with the commit process.
Thank you very much!
*patch
The output of hg diff -g:
diff --git a/src/hotspot/cpu/x86/assembler_x86.cpp
b/src/hotspot/cpu/x86/assembler_x86.cpp
--- a/src/hotspot/cpu/x86/assembler_x86.cpp
+++ b/src/hotspot/cpu/x86/assembler_x86.cpp
@@ -3099,7 +3099,7 @@
}
return;
}
- if (UseAddressNop && VM_Version::is_amd()) {
+ if (UseAddressNop && (VM_Version::is_amd() || VM_Version::is_hygon())) {
//
// Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
// 1: 0x90
diff --git a/src/hotspot/cpu/x86/vm_version_ext_x86.cpp
b/src/hotspot/cpu/x86/vm_version_ext_x86.cpp
--- a/src/hotspot/cpu/x86/vm_version_ext_x86.cpp
+++ b/src/hotspot/cpu/x86/vm_version_ext_x86.cpp
@@ -262,6 +262,34 @@
int VM_Version_Ext::_no_of_cores = 0;
int VM_Version_Ext::_no_of_packages = 0;
+const char* const VM_Version_Ext::_family_id_hygon[] = {
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "Dhyana" //family 18h
+};
+
void VM_Version_Ext::initialize(void) {
ResourceMark rm;
@@ -340,6 +368,10 @@
return !is_amd_Barcelona();
}
+ if (is_hygon()) {
+ return true;
+ }
+
return false;
}
@@ -397,7 +429,7 @@
}
const char* VM_Version_Ext::cpu_family_description(void) {
- int cpu_family_id = extended_cpu_family();
+ uint32_t cpu_family_id = extended_cpu_family();
if (is_amd()) {
return _family_id_amd[cpu_family_id];
}
@@ -407,6 +439,11 @@
}
return _family_id_intel[cpu_family_id];
}
+ if (is_hygon()) {
+ if (cpu_family_id < sizeof(_family_id_hygon)/sizeof(char *))
+ return _family_id_hygon[cpu_family_id];
+ }
+
return "Unknown x86";
}
@@ -423,6 +460,9 @@
} else if (is_amd()) {
cpu_type = "AMD";
x64 = cpu_is_em64t() ? " AMD64" : "";
+ } else if (is_hygon()) {
+ cpu_type = "Hygon";
+ x64 = cpu_is_em64t() ? " AMD64" : "";
} else {
cpu_type = "Unknown x86";
x64 = cpu_is_em64t() ? " x86_64" : "";
diff --git a/src/hotspot/cpu/x86/vm_version_ext_x86.hpp
b/src/hotspot/cpu/x86/vm_version_ext_x86.hpp
--- a/src/hotspot/cpu/x86/vm_version_ext_x86.hpp
+++ b/src/hotspot/cpu/x86/vm_version_ext_x86.hpp
@@ -37,6 +37,7 @@
static const char* const _family_id_intel[];
static const char* const _family_id_amd[];
+ static const char* const _family_id_hygon[];
static const char* const _brand_id[];
static const char* const _model_id_pentium_pro[];
diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp
b/src/hotspot/cpu/x86/vm_version_x86.cpp
--- a/src/hotspot/cpu/x86/vm_version_x86.cpp
+++ b/src/hotspot/cpu/x86/vm_version_x86.cpp
@@ -1165,7 +1165,7 @@
}
}
- if( is_amd() ) { // AMD cpus specific settings
+ if( is_amd() || is_hygon() ) { // AMD cpus specific settings
if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
// Use it on new AMD cpus starting from Opteron.
UseAddressNop = true;
@@ -1239,8 +1239,8 @@
}
#endif // COMPILER2
- // Some defaults for AMD family 17h
- if ( cpu_family() == 0x17 ) {
+ // Some defaults for AMD family 17h || Hygon family 18h
+ if ( cpu_family() == 0x17 || cpu_family() == 0x18 ) {
// On family 17h processors use XMM and UnalignedLoadStores for
Array Copy
if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp
b/src/hotspot/cpu/x86/vm_version_x86.hpp
--- a/src/hotspot/cpu/x86/vm_version_x86.hpp
+++ b/src/hotspot/cpu/x86/vm_version_x86.hpp
@@ -495,13 +495,13 @@
result |= CPU_CX8;
if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
result |= CPU_CMOV;
- if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
+ if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || ((is_amd() ||
is_hygon()) &&
_cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
result |= CPU_FXSR;
// HT flag is set for multi-core processors also.
if (threads_per_core() > 1)
result |= CPU_HT;
- if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
+ if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || ((is_amd() ||
is_hygon()) &&
_cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
result |= CPU_MMX;
if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
@@ -576,8 +576,8 @@
if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
result |= CPU_FMA;
- // AMD features.
- if (is_amd()) {
+ // AMD|Hygon features.
+ if (is_amd() || is_hygon()) {
if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
(_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
result |= CPU_3DNOW_PREFETCH;
@@ -711,6 +711,7 @@
static int cpu_family() { return _cpu;}
static bool is_P6() { return cpu_family() >= 6; }
static bool is_amd() { assert_is_initialized(); return
_cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
+ static bool is_hygon() { assert_is_initialized(); return
_cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
static bool is_intel() { assert_is_initialized(); return
_cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
static bool is_zx() { assert_is_initialized(); return
(_cpuid_info.std_vendor_name_0 == 0x746e6543) ||
(_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
static bool is_atom_family() { return ((cpu_family() == 0x06) &&
((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) ||
(extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
@@ -734,7 +735,7 @@
if (!supports_topology || result == 0) {
result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
}
- } else if (is_amd()) {
+ } else if (is_amd() || is_hygon()) {
result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
} else if (is_zx()) {
bool supports_topology = supports_processor_topology();
@@ -770,7 +771,7 @@
intx result = 0;
if (is_intel()) {
result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
- } else if (is_amd()) {
+ } else if (is_amd() || is_hygon()) {
result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
} else if (is_zx()) {
result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
@@ -857,7 +858,7 @@
// AMD features
static bool supports_3dnow_prefetch() { return (_features &
CPU_3DNOW_PREFETCH) != 0; }
- static bool supports_mmx_ext() { return is_amd() &&
_cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
+ static bool supports_mmx_ext() { return (is_amd()||is_hygon()) &&
_cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
@@ -870,7 +871,7 @@
}
static bool supports_tscinv() {
return supports_tscinv_bit() &&
- ( (is_amd() && !is_amd_Barcelona()) ||
+ ( ((is_amd()||is_hygon()) && !is_amd_Barcelona()) ||
is_intel_tsc_synched_at_init() );
}
@@ -896,7 +897,7 @@
// Core - 256 / prefetchnta
// It will be used only when AllocatePrefetchStyle > 0
- if (is_amd()) { // AMD
+ if (is_amd() || is_hygon()) { // AMD
if (supports_sse2()) {
return 256; // Opteron
} else {
*test
I tested it with jtreg and found no regressions.
Base Run：
==============================
Test summary
==============================
TEST TOTAL PASS FAIL ERROR
jtreg:test/hotspot/jtreg:tier1 1396 1396 0 0
>> jtreg:test/jdk:tier1 1867 1866 1 0 <<
>> jtreg:test/langtools:tier1 3920 3919 1 0 <<
jtreg:test/nashorn:tier1 0 0 0 0
jtreg:test/jaxp:tier1 0 0 0 0
==============================
TEST FAILURE
And The result of after patching is the same as the before.
==============================
Test summary
==============================
TEST TOTAL PASS FAIL ERROR
jtreg:test/hotspot/jtreg:tier1 1396 1396 0 0
>> jtreg:test/jdk:tier1 1867 1866 1 0 <<
>> jtreg:test/langtools:tier1 3920 3919 1 0 <<
jtreg:test/nashorn:tier1 0 0 0 0
jtreg:test/jaxp:tier1 0 0 0 0
==============================
TEST FAILURE
result of testcase TestCPUInformation.java
----------System.out:(15/1604)----------
Event: jdk.CPUInformation {
startTime = 11:10:26.284
cpu = "Hygon Dhyana (HT) SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 SSE4A AMD64"
description = "Brand: Hygon Dhyana Eng Sample , Vendor: HygonGenuine
Family: Dhyana (0x18), Model: <unknown> (0x0), Stepping: 0x2
Ext. family: 0x9, Ext. model: 0x0, Type: 0x0, Signature: 0x00900f02
Features: ebx: 0x06100800, ecx: 0x3cd83209, edx: 0x178bfbff
Ext. features: eax: 0x00900f02, ebx: 0x60000000, ecx: 0x35c233ff, edx:
0x2fd3fbff
Supports: On-Chip FPU, Virtual Mode Extensions, Debugging Extensions,
Page Size Extensions, Time Stamp Counter, Model Specific Registers,
Physical Address Extension, Machine Check Exceptions, CMPXCHG8B
Instruction, On-Chip APIC, Fast
System Call, Memory Type Range Registers, Page Global Enable, Machine
Check Architecture, Conditional Mov Instruction, Page Attribute Table,
36-bit Page Size Extension, CLFLUSH Instruction, Intel Architecture MMX
Technology, Fast Fl
oat Point Save and Restore, Streaming SIMD extensions, Streaming SIMD
extensions 2, Hyper Threading, Streaming SIMD Extensions 3,
MONITOR/MWAIT instructions, Supplemental Streaming SIMD Extensions 3,
Fused Multiply-Add, CMPXCHG16B, S
treaming SIMD extensions 4.1, Streaming SIMD extensions 4.2, MOVBE,
Popcount instruction, XSAVE, OSXSAVE, AVX, F16C, LAHF/SAHF instruction
support, Core multi-processor leagacy mode, Advanced Bit Manipulations:
LZCNT, SSE4A: MOVNTSS,
MOVNTSD, EXTRQ, INSERTQ, Misaligned SSE mode, SYSCALL/SYSRET, Execute
Disable Bit, RDTSCP, Intel 64 Architecture, Invariant TSC"
sockets = 1
cores = 16
hwThreads = 16
}
Is there anything incorrectly?
Please let me know your comments.
Best Regards!
Fanjinke.
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