RFR(m): 8220351: Cross-modifying code

[Andrew Haley]

On 3/13/19 11:07 AM, Robbin Ehn wrote:
> sparc have the same issue as arm, with "flush <address>".
> Adding an indirection to these, so we don't have the oops in the instruction 
> stream, as you suggested, seems like the sane thing to do. But costly.

It depends, I think. In an out-of-order processor with speculation, we
shouldn't see the 4- or 5-cycle latency for the load from L1 cache. I
guess it would hit cache utilization, though. It'd be an interesting
experiment.

-- 
Andrew Haley
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
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