RFR(m): 8220351: Cross-modifying code

[Robbin Ehn]

On 3/14/19 11:03 AM, Andrew Haley wrote:
> On 3/11/19 8:08 AM, Robbin Ehn wrote:
> 
>> For simplicity I'll talk about x86, which have instruction cache
>> coherency.
> 
> I don't think this is the right approach.

I was talking about the example in which I used the x86 native wrapper.
Why this is a problem even on platforms which have coherency.

> 
> You've put fences into shared code, but the semantics to make this
> work correctly are different on different platforms. For example, some
> platforms may not use patching, but instead use the constant
> pool. Some platforms may need cache flushes as well as fences, so the
> solution presented here is either inadequate, inefficient, or both.
> 
The barrier placement, if any barrier is needed, would be the same for all
platforms. So this patch places those barrier where we need them and add
implementation for x86 (and PPC/s390). So for platforms that also need cache
flushes this is inadequate and is not intended to fix that.

/Robbin