[aarch64-port-dev ] RFR: aarch64: minor improvements of atomic operations

[Andrew Haley]

On 11/12/19 5:38 PM, Erik Österlund wrote:
> My hope is that the AArch64 port should use inline assembly as you suggest, so we can see that the generated code is correct, as we wait for the glorious future where all HotSpot code has been rewritten to work with seq_cst (and we are *not* there now).

I don't doubt it. :-)

But my arguments about the C++ intrinsics being well-enough defined,
at least on AArch64 Linux, have not changed, and I'm not going to
argue all that again. I'll grant you that there may well be issues on
various x86 compilers, but that isn't relevant here.

> Now it looks like you have discovered that we sometimes have double trailing dmb ish, and sometimes lacking leading dmb ish if I am reading this right. That seems to make the case stronger,

Sure, we can use inline asm if there's no other way to do it, but I
don't think that's necessary. All we need is to use

  T res;
  __atomic_exchange(dest, &exchange_value, &res, __ATOMIC_RELEASE);
  FULL_MEM_BARRIER;

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
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