AArch64: Neoverse N1 atomic operations and -moutline-atomics

[Andrew Haley]

Seen here:

https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=956418

It looks like there's a Neoverse N1 processor "feature" that leads to
severe performance differences between atomic operations using the
atomic memory instructions (e.g.CAS) and those using Exclusive Loads
and Stores (e.g. LDAXR and STLXR.) The latter can be much slower in
some cases.

Therefore, if we want to avoid severe performance degradation we have
to use atomic memory instructions on Neoverse N1 processors. This has
caused some interesting problems for the authors of libgcc and glibc,
which are statically compiled and do not generate code depending on
the processor in use, as we do in generated code in HotSpot.

The solution, which no-one likes very much, is to get GCC to generate
subroutine calls for all atomic memory operations. The called routines
look like this:

__aarch64_cas4_relax:
 <+0>:     adrp    x16, 0x420000 <__aarch64_have_lse_atomics>
 <+4>:     ldrb    w16, [x16, :lo12:__aarch64_have_lse_atomics]
 <+8>:     cbz     w16, 0x400584 <__aarch64_cas4_relax+20>
 <+12>:    cas     w0, w1, [x2]
 <+16>:    ret
 <+20>:    mov     w16, w0
 <+24>:    ldxr    w0, [x2]
 <+28>:    cmp     w0, w16
 <+32>:    b.ne    0x40059c <__aarch64_cas4_relax+44>
 <+36>:    stxr    w17, w1, [x2]
 <+40>:    cbnz    w17, 0x400588 <__aarch64_cas4_relax+24>
 <+44>:    ret

This is, as you can see, horrible, but but thankfully we don't have to
change AArch64 HotSpot because we use GCC's atomic builtins everywhere
in C++ code. All we'll have to do is compile HotSpot with a new GCC
and we'll be done.

However, we also generate atomic operations. Happily, for some time we
have generated and used atomic memory instructions whenever possible,
so we don't have to change that either.

Yay! Go us.

https://gcc.gnu.org/legacy-ml/gcc-patches/2019-09/msg01036.html

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
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