RFR: 8221554: aarch64 cross-modifying code [v6]

[Andrew Haley]

On Thu, 12 Nov 2020 17:25:41 GMT, Alan Hayward <github.com+4146708+a74nh at openjdk.org> wrote:

>> src/hotspot/share/runtime/orderAccess.hpp line 237:
>> 
>>> 235: // to the instruction code preceding the fence is not reordered w.r.t. any
>>> 236: // memory accesses to instruction code subsequent to the fence in program order.
>>> 237: // It  should be used in conjunction with safepointing to ensure that changes
>> 
>> This is rather misleading: the AArch64 needs the ISB for the instruction pipeline rather than the cache, which is invalidated by the IC IVAU broadcast. I suspect other processors work in the same way.
>> The language in the AArch64 spec is better, IMO:
>> "ensures that all instructions that come after the ISB instruction in program order are fetched from
>> the cache or memory after the ISB instruction has completed"
>
> This better?
> 
> // Finally, we define an "instruction_fence" operation, which ensures that all
> // instructions that come after the ISB instruction in program order are fetched
> // from the cache or memory after the ISB instruction has completed
> // It should be used in conjunction with safepointing to ensure that changes
> // to the instruction stream are seen on exit from a safepoint. Namely:
> .....etc

// Finally, we define an "instruction_fence" operation, which ensures that all
// instructions that come after the fence in program order are fetched
// from the cache or memory after the fence has completed

-------------

PR: https://git.openjdk.java.net/jdk/pull/428