RFR: 8256318: AArch64: Add support for floating-point absolute difference [v4]

[Ningsheng Jian]

On Tue, 17 Nov 2020 06:02:41 GMT, Dong Bo <dongbo at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64_neon.ad line 3462:
>> 
>>> 3460: instruct vabs8B(vecD dst, vecD src)
>>> 3461: %{
>>> 3462:   predicate(n->as_Vector()->length() == 8);
>> 
>> This is different from original code.
>
> For integer absolute (vector), the accepted arrangements are `T8B, T16B, T4H, T8H, T2S, T4S, T2D`.
> ARM compiler armasm user guide reference: https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/ABS--vector-?lang=en
> I think the original code `n->as_Vector()->length() == 4 ||` is not right for basic type Byte. So I delete it, I am sorry if I miss something.

We load 4B with loadV4 but handle 4B types with T8B instructions. And current min_vector_size for byte type is 4, so it's possible for vectorizer to generate 4B vector nodes.

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PR: https://git.openjdk.java.net/jdk/pull/1215