RFR: 8264543: Cross modify fence optimization for x86 [v6]

[Xubo Zhang]

> Intel introduced a new instruction “serialize” which ensures that all modifications to flags, registers, and memory by previous instructions are completed and all buffered writes are drained to memory before the next instruction is fetched and executed. It is a serializing instruction and can be used to implement cross modify fence (OrderAccess::cross_modify_fence_impl) more efficiently than using “cpuid” on supported 32-bit and 64-bit x86 platforms.
> 
> The availability of the SERIALIZE instruction is indicated by the presence of the CPUID feature flag SERIALIZE, bit 14 of the EDX register in sub-leaf CPUID:7H.0H.
> 
> https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Xubo Zhang has updated the pull request incrementally with one additional commit since the last revision:

  fix typo and change to require _MSC_VER >= 1928 to be safe

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Changes:
  - all: https://git.openjdk.java.net/jdk/pull/4848/files
  - new: https://git.openjdk.java.net/jdk/pull/4848/files/427c46ce..e17b37c6

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=jdk&pr=4848&range=05
 - incr: https://webrevs.openjdk.java.net/?repo=jdk&pr=4848&range=04-05

  Stats: 2 lines in 1 file changed: 0 ins; 0 del; 2 mod
  Patch: https://git.openjdk.java.net/jdk/pull/4848.diff
  Fetch: git fetch https://git.openjdk.java.net/jdk pull/4848/head:pull/4848

PR: https://git.openjdk.java.net/jdk/pull/4848