RFR: 8264543: Cross modify fence optimization for x86 [v6]

[David Holmes]

On Mon, 2 Aug 2021 16:17:58 GMT, Xubo Zhang <github.com+58006833+xbzhang99 at openjdk.org> wrote:

>> Intel introduced a new instruction “serialize” which ensures that all modifications to flags, registers, and memory by previous instructions are completed and all buffered writes are drained to memory before the next instruction is fetched and executed. It is a serializing instruction and can be used to implement cross modify fence (OrderAccess::cross_modify_fence_impl) more efficiently than using “cpuid” on supported 32-bit and 64-bit x86 platforms.
>> 
>> The availability of the SERIALIZE instruction is indicated by the presence of the CPUID feature flag SERIALIZE, bit 14 of the EDX register in sub-leaf CPUID:7H.0H.
>> 
>> https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
>
> Xubo Zhang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fix typo and change to require _MSC_VER >= 1928 to be safe

Thanks Xubo, I will run this through our test system using VS 2019 and VS 2017 before approving. You will still need a second reviewer after that.

David

-------------

PR: https://git.openjdk.java.net/jdk/pull/4848