RFC: AArch64: Implementing spin pauses with ISB

[Andrew Haley]

On 8/18/21 11:22 PM, Stuart Monteith wrote:
> I don't think WFE will work for you - I found on at least one machine the cpu will pause more or less indefinitely.

That's a shame. I thought it was specified to awaken when the exclusive monitor
was cleared, which will happen when the exclusive location is written to, won't
it?

> The 
> SEV instruction may be a blunt weapon as it applies to all cores on the CPU.
> 
> This discussion appears split between the Spin Pause review and this email thread, but the idea of the implementation 
> being switchable is appealing. Hypothetically the options might be NONE, NOP, ISB, YIELD. With the current semantics, 
> YIELD could be theoretically useful on SMT cores, but I don't know if that would change in the future to be applicable 
> more widely.

Mmm, yes. I think it should be easy enough to make it switchable. I'd
support that, I think.

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671