RFR: 8261649: AArch64: Optimize LSE atomics in C++ code

[Andrew Dinn]

On Thu, 18 Feb 2021 09:20:21 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.S line 75:
>> 
>>> 73:         .align 5
>>> 74: aarch64_atomic_cmpxchg_1_default_impl:
>>> 75:         dmb     ish
>> 
>> Having argued above that this dmb is never needed why is it in this default impl? (also for size 4 and 8)
>
> The default impl uses  ARMv8 LDXR ... STXR but the DMB is not needed if and only if ARMv8.1 LSE instructions.

Doh! And it says that clearly in the comment. Ok.

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PR: https://git.openjdk.java.net/jdk/pull/2611