RFR: 8260025: HotSpot cannot identify Zen (family 17h) processor

David Holmes david.holmes at oracle.com
Wed Jan 20 12:04:58 UTC 2021


On 20/01/2021 6:18 pm, Yasumasa Suenaga wrote:
> On Wed, 20 Jan 2021 08:03:25 GMT, David Holmes <dholmes at openjdk.org> wrote:
> 
>>> HotSpot cannot identify Zen (family 17h) processor. You can see this problem in flight record as below:
>>>
>>> java -XX:StartFlightRecording=filename=test.jfr --version
>>>
>>> `(null)` in `cpu` and `<unknown>` in `Family` should be `Zen`.
>>>
>>> $ jfr print --events jdk.CPUInformation test.jfr
>>> jdk.CPUInformation {
>>>    startTime = 15:59:37.207
>>>    cpu = "AMD (null) (HT) SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 SSE4A AMD64"
>>>    description = "Brand: AMD Ryzen 3 3300X 4-Core Processor , Vendor: AuthenticAMD
>>> Family: <unknown> (0x17), Model: <unknown> (0x71), Stepping: 0x0
>>> Ext. family: 0x8, Ext. model: 0x7, Type: 0x0, Signature: 0x00870f10
>>> Features: ebx: 0x00020800, ecx: 0xfed83203, edx: 0x178bfbff
>>> Ext. features: eax: 0x00870f10, ebx: 0x20000000, ecx: 0x004003f3, edx: 0x2fd3fbff
>>> Supports: On-Chip FPU, Virtual Mode Extensions, Debugging Extensions, Page Size Extensions, Time Stamp Counter, Model Specific Registers, Physical Address Extension, Machine Check Exceptions, CMPXCHG8B Instruction, On-Chip APIC, Fast System Call, Memory Type Range Registers, Page Global Enable, Machine Check Architecture, Conditional Mov Instruction, Page Attribute Table, 36-bit Page Size Extension, CLFLUSH Instruction, Intel Architecture MMX Technology, Fast Float Point Save and Restore, Streaming SIMD extensions, Streaming SIMD extensions 2, Hyper Threading, Streaming SIMD Extensions 3, PCLMULQDQ, Supplemental Streaming SIMD Extensions 3, Fused Multiply-Add, CMPXCHG16B, Streaming SIMD extensions 4.1, Streaming SIMD extensions 4.2, MOVBE, Popcount instruction, AESNI, XSAVE, OSXSAVE, AVX, F16C, LAHF/SAHF instruction support, Core multi-processor leagacy mode, Advanced Bit Manipulations: LZCNT, SSE4A: MOVNTSS, MOVNTSD, EXTRQ, INSERTQ, Misaligned SSE mode, SYSCALL/SYSRET, Execute Di
>   sable Bit, RDTSCP, Intel 64 Architecture"
>>>    sockets = 1
>>>    cores = 2
>>>    hwThreads = 2
>>> }
>>>
>>> It is caused by missing comma after `Opteron QC/Phenom`. So I think the fix is trivial.
>>
>> Hi Yasumasa,
>>
>> You should have led with the fact this is caused by a missing comma! IIUC this will shorten the array by one entry and so Zen will be in the wrong position.
>>
>> Looks good and trivial.
>>
>> Thanks,
>> David
> 
> Thanks @dholmes-ora and @tstuefe for the review!
> 
>> You should have led with the fact this is caused by a missing comma!
> 
> Do you mean we should change the subject like "Missing comma in VM_Version_Ext::_family_id_amd"?

Well yes, the bug report could have been clearer :) I went from the bug 
report to the PR link and straight to "Files changed" to do the review - 
after checking that we did in fact have Zen support. So I never saw the 
"It is caused by missing comma ..." you added for the PR description.

Cheers,
David
-----

>> IIUC this will shorten the array by one entry and so Zen will be in the wrong position.
> 
> Yes, "Zen" was located at penultimate position, and NULL was set to the tail when I checked it on GDB.
> 
> -------------
> 
> PR: https://git.openjdk.java.net/jdk/pull/2158
> 


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