[jdk16] RFR: 8260585: AArch64: Wrong code generated for shifting right and accumulating four unsigned short integers [v2]

[Andrew Haley]

On 1/30/21 5:07 AM, Dong Bo wrote:
> On Fri, 29 Jan 2021 20:31:16 GMT, Vladimir Kozlov <kvn at openjdk.org> wrote:
> 
>>> Why didn't the testing for JDK-8255949 catch this?  Do you need to fix the regression test too?
>>
>> Yes, we need regression test for this fix. Or modify existing one to catch it.
> 
> Did not run local tests for small loops in JDK-8255949.
> Updated a test for all shift and accumulating operations which can catch this.
> 
> -------------
> 
> PR: https://git.openjdk.java.net/jdk16/pull/136

I don't understand. Looking at this:

instruct vsrla4S_imm(vecD dst, vecD src, immI shift) %{
  predicate(n->as_Vector()->length() == 4);
  match(Set dst (AddVS dst (URShiftVS src (RShiftCntV shift))));
  ins_cost(INSN_COST);
  format %{ "usra    $dst, $src, $shift\t# vector (4H)" %}
  ins_encode %{
    int sh = (int)$shift$$constant;
    if (sh >= 16) {
      __ eor(as_FloatRegister($src$$reg), __ T8B,
             as_FloatRegister($src$$reg),
             as_FloatRegister($src$$reg));
    } else {
      __ usra(as_FloatRegister($dst$$reg), __ T4H,
             as_FloatRegister($src$$reg), sh);
    }
  %}
  ins_pipe(vshift64_imm);
%}

What happens when the shift is >= 16? What happens to src and dst?

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
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