RFR: 8264543: Cross modify fence optimization for x86 [v2]

[David Holmes]

On Thu, 27 May 2021 17:36:24 GMT, Xubo Zhang <github.com+58006833+xbzhang99 at openjdk.org> wrote:

>> Intel introduced a new instruction “serialize” which ensures that all modifications to flags, registers, and memory by previous instructions are completed and all buffered writes are drained to memory before the next instruction is fetched and executed. It is a serializing instruction and can be used to implement cross modify fence (OrderAccess::cross_modify_fence_impl) more efficiently than using “cpuid” on supported 32-bit and 64-bit x86 platforms.
>> 
>> The availability of the SERIALIZE instruction is indicated by the presence of the CPUID feature flag SERIALIZE, bit 14 of the EDX register in sub-leaf CPUID:7H.0H.
>> 
>> https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
>
> Xubo Zhang has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains one commit:
> 
>   8264543: Using Intel serialize instruction to replace cpuid in Cross modify fence, on supported platforms
>   rebase with master

Hi,

Thanks for the additional benchmarking numbers. This seems fine in principle as previously stated but should be done for all x86 not just Linux. Other changes requested below.

Thanks,
David

src/hotspot/os_cpu/linux_x86/os_linux_x86.cpp line 461:

> 459: }
> 460: 
> 461: bool os::supports_serialize(){

This function is unnecessary and pollutes the OS namespace with something that is not OS related. Just use VM_Version::supports_serialize() directly.

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Changes requested by dholmes (Reviewer).

PR: https://git.openjdk.java.net/jdk/pull/3334