RFR: 8262519: AArch64: Unnecessary acquire semantics of memory-order-conservative atomics in C++ Hotspot code

[Dong Bo]

On Tue, 2 Mar 2021 12:52:59 GMT, Dong Bo <dongbo at openjdk.org> wrote:

>> I don't want to see this go in, for two reasons. Firstly, barrier-ordered-before only applies to atomic instructions with both acquire *and* release semantics, as the comment says. So we cannot rely on that guarantee, and we'd need some much more detailed analysis to make this changes. Secondly, the architecture specification is being revised, and the result will hopefully be that we can get a better version than this. So please, leave this alone for now.
>
> OKAY, this make sense to us.
> 
> If it is OK to keep the exclusive part of this patch? :-)
> As far as we know, the exclusive instructions are not being revised.
> And we see `ldxr+stxlr+dmb` have been used in linux kernel since 2014 [1], and still used by now [2].
> 
> [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/1391516953-14541-1-git-send-email-will.deacon@arm.com/
> [2] https://github.com/torvalds/linux/blob/7a7fd0de4a9804299793e564a555a49c1fc924cb/arch/arm64/include/asm/atomic_ll_sc.h#L102

BTW, the barrier-ordered-before applies with stlxr according to the architecture specification:
...
any of the following cases apply:
...
RW2 is a write W2 and either:
— RW1 is a write W1 appearing in program order before a DMB ST that appears in program
order before W2.
— **W2 is generated by an instruction with Release semantics.**

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PR: https://git.openjdk.java.net/jdk/pull/2788