RFR: 8262519: AArch64: Unnecessary acquire semantics of memory-order-conservative atomics in C++ Hotspot code

[Andrew Haley]

On Thu, 4 Mar 2021 09:33:18 GMT, Dong Bo <dongbo at openjdk.org> wrote:

>>> Without the acquire, the loads/stores after the atomic operations still can not pass the `dmb`.
>>> Remove the acquire does not change the order between preceding loads/stores and `stlxr`.
>> 
>> Looks like it. I tried this example, which makes sure that a preceding store does not pass the load in LDXR;STLXR;DMB :
>> 
>>  MOConservative
>> { 0:X0=a; 0:X1=b; 1:X0=a; 1:X1=b; a=0; b=0; }
>> P0 | P1;
>> MOV W3, #1 | MOV W3, #1;
>> STLR W3, [X0] | STR W3, [X1];
>> LDAR W1, [X1] | LDXR W1, [X0];
>>               | STLXR W5, W4, [X0];
>>               | CBZ W5, FOO;
>>               | MOV W1, #99;
>>               | FOO: ;
>>               | DMB ISH;
>> exists
>> (0:X1=0 /\ 1:X1 = 0)
>> 
>> I don't think a preceding load can be reordered with the ```ldxr``` either, but I haven't written that test.
>
>> > Without the acquire, the loads/stores after the atomic operations still can not pass the `dmb`.
>> > Remove the acquire does not change the order between preceding loads/stores and `stlxr`.
>> 
>> Looks like it. I tried this example, which makes sure that a preceding store does not pass the load in LDXR;STLXR;DMB :
>> 
>> ```
>> { 0:X0=a; 0:X1=b; 1:X0=a; 1:X1=b; a=0; b=0; }
>> P0 | P1;
>> MOV W3, #1 | MOV W3, #1;
>> STLR W3, [X0] | STR W3, [X1];
>> LDAR W1, [X1] | LDXR W1, [X0];
>>               | STLXR W5, W4, [X0];
>>               | CBZ W5, FOO;
>>               | MOV W1, #99;
>>               | FOO: ;
>>               | DMB ISH;
>> exists
>> (0:X1=0 /\ 1:X1 = 0)
>> ```
>> 
>> I don't think a preceding load can be reordered with the `ldxr` either, but I haven't written that test.
> 
> Hi, I tried the example below to verify the order of preceding load as mentioned:
> AArch64 ExclusiveRead
> { 0:X8=a; 0:X9=b; 1:X8=a; 1:X9=b; a=1; b=1; }
> P0            | P1                 ;
> MOV W3, #3    | LDR W3, [X9]       ;
> MOV W4, #5    | LDXR W1, [X8]      ;
> STR W3, [X8]  | STLXR W5, W4, [X8] ;
> STLR W4, [X9] | CBZ W5, FOO        ;
>               | MOV W1, #99        ;
>               | FOO:               ;
>               | DMB ISH            ;
> exists
> (1:X1=1 /\ 1:X3=5)
> No `1:X1=1 /\ 1:X3=5` witnessed.

And this one (I think) makes sure that there is a total order of stores:

AArch64 SeqCst
{ 0:X0=a; 0:X1=b; 1:X0=a; 1:X1=b; a=0; b=0; }
P0 | P1;
MOV W3, #1          | MOV W3, #1;
MOV W8, #99         | MOV W8, #99 ;
STR W3, [X0]        | STR W3, [X1];
LDXR W2, [X1]       | LDXR W2, [X0];
STLXR W5, W8, [X1]  | STLXR W5, W8, [X0]  ;
CBZ W5, FOO         | CBZ W5, FOO1        ;
MOV W2, #1234       | MOV W2, #1234        ;
FOO:                | FOO1:               ;
DMB ST              | DMB ST             ;
exists
(0:X2=0 /\ 1:X2 = 0)

Test SeqCst Allowed
States 8
0:X2=0; 1:X2=1;
0:X2=0; 1:X2=1234;
0:X2=1; 1:X2=0;
0:X2=1; 1:X2=1;
0:X2=1; 1:X2=1234;
0:X2=1234; 1:X2=0;
0:X2=1234; 1:X2=1;
0:X2=1234; 1:X2=1234;
No
Witnesses
Positive: 0 Negative: 15
Condition exists (0:X2=0 /\ 1:X2=0)
Observation SeqCst Never 0 15

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PR: https://git.openjdk.java.net/jdk/pull/2788