RFR: 8262491: AArch64: CPU description should contain compatible board list [v8]

[Andrew Haley]

On Wed, 10 Mar 2021 23:47:27 GMT, Yasumasa Suenaga <ysuenaga at openjdk.org> wrote:

>> HotSpot generates CPU description when it is started. We can see it `jdk.CPUInformation` JFR event as below:
>> 
>> $ jfr print --events jdk.CPUInformation raspi4.jfr
>> jdk.CPUInformation {
>>   startTime = 22:57:13.521
>>   cpu = "AArch64"
>>   description = "AArch64 0x41:0x0:0xd08:3, simd, crc"
>>   sockets = 4
>>   cores = 4
>>   hwThreads = 4
>> }
>> 
>> `description` contains "AArch64", it is fixed value, we cannot guess the process was run on what machine (SoC).
>> 
>> In Linux, we can use `compatible`property in device tree to guess the machine. The 'compatible' property contains a sorted list of strings starting with the exact name of the machine, followed by an optional list of boards it is compatible with sorted from most compatible to least.
>> 
>> After this change, we can get the description as below:
>> 
>> jdk.CPUInformation {
>>   startTime = 00:32:49.767
>>   cpu = "AArch64"
>>   description = "raspberrypi,4-model-b brcm,bcm2711 0x41:0x0:0xd08:3, simd, crc"
>>   sockets = 4
>>   cores = 4
>>   hwThreads = 4
>> }
>> 
>> In Linux on AMD64, we can see as following, then we can guess the CPU model from it. The same should do for AArch64.
>> 
>> jdk.CPUInformation {
>>   startTime = 17:28:03.907
>>   cpu = "AMD (null) (HT) SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 SSE4A AMD64"
>>   description = "Brand: AMD Ryzen 3 3300X 4-Core Processor , Vendor: AuthenticAMD
>> Family: <unknown> (0x17), Model: <unknown> (0x71), Stepping: 0x0
>> Ext. family: 0x8, Ext. model: 0x7, Type: 0x0, Signature: 0x00870f10
>> Features: ebx: 0x01020800, ecx: 0xfed83203, edx: 0x178bfbff
>> Ext. features: eax: 0x00870f10, ebx: 0x20000000, ecx: 0x004003f3, edx: 0x2fd3fbff
>> Supports: On-Chip FPU, Virtual Mode Extensions, Debugging Extensions, Page Size Extensions, Time Stamp Counter, Model Specific Registers, Physical Address Extension, Machine Check Exceptions, CMPXCHG8B Instruction, On-Chip APIC, Fast System Call, Memory Type Range Registers, Page Global Enable, Machine Check Architecture, Conditional Mov Instruction, Page Attribute Table, 36-bit Page Size Extension, CLFLUSH Instruction, Intel Architecture MMX Technology, Fast Float Point Save and Restore, Streaming SIMD extensions, Streaming SIMD extensions 2, Hyper Threading, Streaming SIMD Extensions 3, PCLMULQDQ, Supplemental Streaming SIMD Extensions 3, Fused Multiply-Add, CMPXCHG16B, Streaming SIMD extensions 4.1, Streaming SIMD extensions 4.2, MOVBE, Popcount instruction, AESNI, XSAVE, OSXSAVE, AVX, F16C, LAHF/SAHF instruction support, Core multi-processor leagacy mode, Advanced Bit Manipulations: LZCNT, SSE4A: MOVNTSS, MOVNTSD, EXTRQ, INSERTQ, Misaligned SSE mode, SYSCALL/SYSRET, Execute Di
 sable Bit, RDTSCP, Intel 64 Architecture"
>>   sockets = 1
>>   cores = 2
>>   hwThreads = 2
>> }
>
> Yasumasa Suenaga has updated the pull request incrementally with one additional commit since the last revision:
> 
>   refactoring

Marked as reviewed by aph (Reviewer).

-------------

PR: https://git.openjdk.java.net/jdk/pull/2759