RFR: 8266332: Adler32 intrinsic for x86 64-bit platforms [v5]

[Jatin Bhateja]

On Tue, 4 May 2021 00:53:17 GMT, Xubo Zhang <github.com+58006833+xbzhang99 at openjdk.org> wrote:

>> Implement Adler32 intrinsic for x86 64-bit platform using vector instructions.
>> 
>> For the following benchmark:
>> http://cr.openjdk.java.net/~pli/rfr/8216259/TestAdler32.java
>> 
>> The optimization shows ~5x improvement.
>> 
>> Base:
>> Benchmark (count) Mode Cnt Score Error Units
>> TestAdler32Perf.testAdler32Update 64 avgt 25 0.084 ± 0.001 us/op
>> TestAdler32Perf.testAdler32Update 128 avgt 25 0.104 ± 0.001 us/op
>> TestAdler32Perf.testAdler32Update 256 avgt 25 0.146 ± 0.002 us/op
>> TestAdler32Perf.testAdler32Update 512 avgt 25 0.226 ± 0.002 us/op
>> TestAdler32Perf.testAdler32Update 1024 avgt 25 0.390 ± 0.005 us/op
>> TestAdler32Perf.testAdler32Update 2048 avgt 25 0.714 ± 0.007 us/op
>> TestAdler32Perf.testAdler32Update 4096 avgt 25 1.359 ± 0.014 us/op
>> TestAdler32Perf.testAdler32Update 8192 avgt 25 2.751 ± 0.023 us/op
>> TestAdler32Perf.testAdler32Update 16384 avgt 25 5.494 ± 0.077 us/op
>> TestAdler32Perf.testAdler32Update 32768 avgt 25 11.058 ± 0.160 us/op
>> TestAdler32Perf.testAdler32Update 65536 avgt 25 22.198 ± 0.319 us/op
>> 
>> 
>> With patch:
>> Benchmark (count) Mode Cnt Score Error Units
>> TestAdler32Perf.testAdler32Update 64 avgt 25 0.020 ± 0.001 us/op
>> TestAdler32Perf.testAdler32Update 128 avgt 25 0.025 ± 0.001 us/op
>> TestAdler32Perf.testAdler32Update 256 avgt 25 0.031 ± 0.001 us/op
>> TestAdler32Perf.testAdler32Update 512 avgt 25 0.048 ± 0.001 us/op
>> TestAdler32Perf.testAdler32Update 1024 avgt 25 0.078 ± 0.001 us/op
>> TestAdler32Perf.testAdler32Update 2048 avgt 25 0.139 ± 0.002 us/op
>> TestAdler32Perf.testAdler32Update 4096 avgt 25 0.262 ± 0.004 us/op
>> TestAdler32Perf.testAdler32Update 8192 avgt 25 0.524 ± 0.010 us/op
>> TestAdler32Perf.testAdler32Update 16384 avgt 25 1.017 ± 0.022 us/op
>> TestAdler32Perf.testAdler32Update 32768 avgt 25 2.058 ± 0.052 us/op
>> TestAdler32Perf.testAdler32Update 65536 avgt 25 3.994 ± 0.013 us/op
>
> Xubo Zhang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   added align; replace incl with addptr

src/hotspot/cpu/x86/assembler_x86.cpp line 7859:

> 7857: void Assembler::vbroadcastf128(XMMRegister dst, Address src, int vector_len) {
> 7858:   assert(VM_Version::supports_avx(), "");
> 7859:   assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");

If you expect vector length 512 bits then above assert should also check for evex mode.

src/hotspot/cpu/x86/macroAssembler_x86.cpp line 3248:

> 3246: 
> 3247: void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
> 3248:   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");

Assert message needs re-composition.

src/hotspot/cpu/x86/macroAssembler_x86_adler.cpp line 85:

> 83:       align(32);
> 84:       bind(SLOOP1A);
> 85:       vbroadcastf128(ydata, Address(data, 0), Assembler::AVX_256bit);

Loop operates over integral data (double word), shouldn't it be safe to use double broadcasting instruction to save which domain switchover penalty (not sure if broadcasting will causes domain switch over though), but this is happening in the main vector loop so being conservative.

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PR: https://git.openjdk.java.net/jdk/pull/3806