RFR: 8264543: Cross modify fence optimization for x86

[Gerard Ziemski]

On Thu, 8 Apr 2021 15:29:56 GMT, Gerard Ziemski <gziemski at openjdk.org> wrote:

>> Intel introduced a new instruction “serialize” which ensures that all modifications to flags, registers, and memory by previous instructions are completed and all buffered writes are drained to memory before the next instruction is fetched and executed. It is a serializing instruction and can be used to implement cross modify fence (OrderAccess::cross_modify_fence_impl) more efficiently than using “cpuid” on supported 32-bit and 64-bit x86 platforms.
>> 
>> The availability of the SERIALIZE instruction is indicated by the presence of the CPUID feature flag SERIALIZE, bit 14 of the EDX register in sub-leaf CPUID:7H.0H.
>> 
>> https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
>
> If this is an optimization, do you have any numbers that show an improvement with this change?

> @gerard-ziemski Hi, could you review the patch? thanks.

Sorry xbzhang99, I do not know enough x86 assembly to actually review it.

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PR: https://git.openjdk.java.net/jdk/pull/3334