RFR: 8264543: Cross modify fence optimization for x86 [v2]

[Kim Barrett]

On Thu, 27 May 2021 17:36:24 GMT, Xubo Zhang <github.com+58006833+xbzhang99 at openjdk.org> wrote:

>> Intel introduced a new instruction “serialize” which ensures that all modifications to flags, registers, and memory by previous instructions are completed and all buffered writes are drained to memory before the next instruction is fetched and executed. It is a serializing instruction and can be used to implement cross modify fence (OrderAccess::cross_modify_fence_impl) more efficiently than using “cpuid” on supported 32-bit and 64-bit x86 platforms.
>> 
>> The availability of the SERIALIZE instruction is indicated by the presence of the CPUID feature flag SERIALIZE, bit 14 of the EDX register in sub-leaf CPUID:7H.0H.
>> 
>> https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
>
> Xubo Zhang has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains one commit:
> 
>   8264543: Using Intel serialize instruction to replace cpuid in Cross modify fence, on supported platforms
>   rebase with master

Just a drive-by comment, not a review.

This change is (necessarily) kind of messy because of the needed low-level
conditionalization.  So it really ought to be supported by benchmark data to
argue that it's worth the effort, both now and in future maintenance.

If the performance impact of this change makes it worth doing, then it
probably ought not be limited to Linux, but should be done for all OS's that
run on x86.

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PR: https://git.openjdk.java.net/jdk/pull/3334