RFR: 8274179: AArch64: Support SVE operations with encodable immediates [v4]

[Nick Gasson]

On Fri, 29 Oct 2021 09:24:47 GMT, Fei Gao <duke at openjdk.java.net> wrote:

>> for(int i = 0; i < LENGTH; i++) {
>>       c[i] = a[i] + 2;
>>     }
>> 
>> For the case showed above, after superword optimization with SVE,
>> without the patch, the vector add operation always has 2 z-reg inputs,
>> like:
>> mov     z16.s, #2
>> add	z17.s, z17.s, z16.s
>> 
>> Considering sve has supported basic binary operations with immediate,
>> this pattern could be further optimized to:
>> add     z16.s, z16.s, #2
>> 
>> To implement it, we added some new match rules and assembler rules in
>> the aarch64 backend. We also made some extensions on immediate types
>> and functions to keep backward compatible.
>> 
>> With the patch, only these binary integer vector operations, +(add),
>> -(sub), &(and), |(orr), and ^(eor) with immediate are supported for
>> the optimization. Other vector operations are not supported currently.
>> 
>> Tested tier1 and test/hotspot/jtreg/compiler on SVE featured AArch64
>> CPU, no new failure.
>> 
>> There is no obvious performance uplift but it can help remove one
>> redundant mov instruction.
>
> Fei Gao has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Add some assertion lines for help functions
>   
>   Change-Id: Ic9120902bd8f8a8ead2e3740435a40f35d21757c

Marked as reviewed by ngasson (Reviewer).

-------------

PR: https://git.openjdk.java.net/jdk/pull/6115