RFR: 8274179: AArch64: Support SVE operations with encodable immediates

[Fei Gao]

On Tue, 26 Oct 2021 11:37:23 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> for(int i = 0; i < LENGTH; i++) {
>>       c[i] = a[i] + 2;
>>     }
>> 
>> For the case showed above, after superword optimization with SVE,
>> without the patch, the vector add operation always has 2 z-reg inputs,
>> like:
>> mov     z16.s, #2
>> add	z17.s, z17.s, z16.s
>> 
>> Considering sve has supported basic binary operations with immediate,
>> this pattern could be further optimized to:
>> add     z16.s, z16.s, #2
>> 
>> To implement it, we added some new match rules and assembler rules in
>> the aarch64 backend. We also made some extensions on immediate types
>> and functions to keep backward compatible.
>> 
>> With the patch, only these binary integer vector operations, +(add),
>> -(sub), &(and), |(orr), and ^(eor) with immediate are supported for
>> the optimization. Other vector operations are not supported currently.
>> 
>> Tested tier1 and test/hotspot/jtreg/compiler on SVE featured AArch64
>> CPU, no new failure.
>> 
>> There is no obvious performance uplift but it can help remove one
>> redundant mov instruction.
>
> I'd like you to split this patch into two parts, please.
> First, please use the new functions such as `Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm)` only for SVE, leaving the existing logic in `Assembler` entirely untouched. This will cause some duplication, but that's OK. We can review changes to merge functionality in a separate patch. This will be much easier.

Thanks :) @theRealAph

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PR: https://git.openjdk.java.net/jdk/pull/6115