RFR: 8274179: AArch64: Support SVE operations with encodable immediates

[Fei Gao]

for(int i = 0; i < LENGTH; i++) {
      c[i] = a[i] + 2;
    }

For the case showed above, after superword optimization with SVE,
without the patch, the vector add operation always has 2 z-reg inputs,
like:
mov     z16.s, #2
add	z17.s, z17.s, z16.s

Considering sve has supported basic binary operations with immediate,
this pattern could be further optimized to:
add     z16.s, z16.s, #2

To implement it, we added some new match rules and assembler rules in
the aarch64 backend. We also made some extensions on immediate types
and functions to keep backward compatible.

With the patch, only these binary integer vector operations, +(add),
-(sub), &(and), |(orr), and ^(eor) with immediate are supported for
the optimization. Other vector operations are not supported currently.

Tested tier1 and test/hotspot/jtreg/compiler on SVE featured AArch64
CPU, no new failure.

There is no obvious performance uplift but it can help remove one
redundant mov instruction.

-------------

Commit messages:
 - 8274179: AArch64: Support SVE operations with encodable immediates

Changes: https://git.openjdk.java.net/jdk/pull/6115/files
 Webrev: https://webrevs.openjdk.java.net/?repo=jdk&pr=6115&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8274179
  Stats: 1496 lines in 14 files changed: 1312 ins; 50 del; 134 mod
  Patch: https://git.openjdk.java.net/jdk/pull/6115.diff
  Fetch: git fetch https://git.openjdk.java.net/jdk pull/6115/head:pull/6115

PR: https://git.openjdk.java.net/jdk/pull/6115