RFR: 8275718: Relax memory constraint on exception counter updates

[David Holmes]

On 31/10/2021 6:39 am, Zhengyu Gu wrote:
> On Mon, 25 Oct 2021 00:22:47 GMT, David Holmes <dholmes at openjdk.org> wrote:
> 
>> What does this achieve? These are not "hot" counters so performance is of zero concern. The conservative memory ordering doesn't guarantee cross-thread visibility but it does seem to me there is less likelihood of error reporting seeing a stale value from another thread if we have "conservative" memory ordering (which traditionally should have been a full bi-directional fence for atomic r-m-w operations).
>>
>> David
> 
> Hi David,
> 
> I agree that they are not "hot" counters, but I disagree that "conservative" memory ordering provides any benefits that prevent other threads from reading stale values.
> 
> We had internal discussion on this topic, Aleksey pointed out:
> "All modifications to any particular atomic variable occur in a total order that is specific to this one atomic variable". This guarantee holds even for relaxed atomic load/stores. This is a very basic guarantee.
> 
> In short, value updated via atomic r-m-w operation should be visible to other threads guaranteed by coherence protocol

I don't know where this guarantee is coming from. Two r-m-w atomic ops 
must have some guarantee via coherence for the atomic op to actually 
work. And an implementation could make any atomic r-m-w implementation 
ensure global immediate visibility. But you cannot assume this is 
guaranteed for all hardware. Even for a given platform this would need 
to be a specified guarantee in the architecture manual, not just 
something deduced/inferred by reasoning.

Cheers,
David
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> PR: https://git.openjdk.java.net/jdk/pull/6065
>