RFR: 8290082: [PPC64] ZGC C2 load barrier stub needs to preserve vector registers [v2]

[Richard Reingruber]

On Tue, 12 Jul 2022 08:02:51 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

> Thanks for looking at it! VSRs are not separate registers. They contain the
> regular FPRs (mapped to 0-31) and VRs (mapped to 32-63). FPRs are managed
> separately while the VRs are not defined elsewhere in the ppc.ad file.

Thanks. I think this should be better explained in register_ppc.hpp.

> There are instructions which operate on VSRs and can access FPRs and VRs. This
> was tricky to implement in hotspot
> ([JDK-8188139](https://bugs.openjdk.org/browse/JDK-8188139) and many follow-up
> fixes). Only the VRs VR0-VR19 are volatile (see register_ppc.hpp), so only
> these ones need spilling. (Same is done for other register types.) VR0-VR19 =
> VSR32-VSR51
> Note that only these ones are currently used by C2 (see `reg_class
> vs_reg` in ppc.ad). Reason is that we currently don't preserve the
> non-volatile ones in the Java entry frame.

I see. VSR52-VSR64 are declared SOC in ppc.ad. Shouldn't they be SOE then?

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PR: https://git.openjdk.org/jdk/pull/9453