RFR: 8290280: riscv: Clean up stack and register handling in interpreter

[Feilong Jiang]

As [JDK-8288971](https://bugs.openjdk.org/browse/JDK-8288971) described, we have the same issue on riscv backend:

1. We use x30 to pass the caller's SP to a callee through adapters. x30 is not a callee-saved register in native ABI [1], we choose x19 for this patch.
2. We frequently recalculate the location where the native SP needs to go. We have a spare slot in the interpreter frame, so we should calculate it once, when the frame is created, and use it.
3. Relate to 1, we should clearly label all the places where the caller's SP is passed to a callee.

[1]. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc

Additional tests:
- hotspot/jdk tier1 on  QEMU with Release JDK
- hotspot tier1 on HiFive Unmatched board with Release JDK
- hotspot tier1 on QEMU with Fastdebug JDK

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Commit messages:
 - riscv: Clean up stack and register handling in interpreter

Changes: https://git.openjdk.org/jdk/pull/9487/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=9487&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8290280
  Stats: 145 lines in 11 files changed: 69 ins; 34 del; 42 mod
  Patch: https://git.openjdk.org/jdk/pull/9487.diff
  Fetch: git fetch https://git.openjdk.org/jdk pull/9487/head:pull/9487

PR: https://git.openjdk.org/jdk/pull/9487