RFR: 8290280: riscv: Clean up stack and register handling in interpreter [v3]

[Feilong Jiang]

> As [JDK-8288971](https://bugs.openjdk.org/browse/JDK-8288971) described, we have the same issue on riscv backend:
> 
> 1. We use x30 to pass the caller's SP to a callee through adapters. x30 is not a callee-saved register in native ABI [1], we choose x19 for this patch.
> 2. We frequently recalculate the location where the native SP needs to go. We have a spare slot in the interpreter frame, so we should calculate it once, when the frame is created, and use it.
> 3. Relate to 1, we should clearly label all the places where the caller's SP is passed to a callee.
> 
> [1]. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
> 
> Additional tests:
> - hotspot/jdk tier1 on  QEMU with Release JDK
> - hotspot tier1 on HiFive Unmatched board with Release JDK
> - hotspot tier1 on QEMU with Fastdebug JDK

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  more unnecessary mv sp to tmp register

-------------

Changes:
  - all: https://git.openjdk.org/jdk/pull/9487/files
  - new: https://git.openjdk.org/jdk/pull/9487/files/c5f8886a..edf203fd

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=9487&range=02
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=9487&range=01-02

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.org/jdk/pull/9487.diff
  Fetch: git fetch https://git.openjdk.org/jdk pull/9487/head:pull/9487

PR: https://git.openjdk.org/jdk/pull/9487