RFR: 8290280: riscv: Clean up stack and register handling in interpreter [v4]

[Fei Yang]

On Fri, 15 Jul 2022 08:54:59 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> As [JDK-8288971](https://bugs.openjdk.org/browse/JDK-8288971) described, we have the same issue on riscv backend:
>> 
>> 1. We use x30 to pass the caller's SP to a callee through adapters. x30 is not a callee-saved register in native ABI [1], we choose x19 for this patch.
>> 2. We frequently recalculate the location where the native SP needs to go. We have a spare slot in the interpreter frame, so we should calculate it once, when the frame is created, and use it.
>> 3. Relate to 1, we should clearly label all the places where the caller's SP is passed to a callee.
>> 
>> [1]. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
>> 
>> Additional tests:
>> - hotspot/jdk tier1 on  QEMU with Release JDK
>> - hotspot tier1 on HiFive Unmatched board with Release JDK
>> - hotspot tier1 on QEMU with Fastdebug JDK
>> - jtreg full on QEMU with Release JDK
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fix

Updated changes looks good.

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Marked as reviewed by fyang (Reviewer).

PR: https://git.openjdk.org/jdk/pull/9487