RFR: JDK-8290137: riscv: small refactoring for add_memory_int32/64

[Aleksey Shipilev]

On Mon, 18 Jul 2022 11:35:09 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.cpp line 60:
>> 
>>> 58: #ifndef PRODUCT
>>> 59:   if (PrintC1Statistics) {
>>> 60:     __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
>> 
>> Is it really `incrementw`, though? These counter fields are `int`-s, are they still 32-bit on RISC-V? If so, shouldn't it be `incrementl`?
>
> @shipilev : Yes, the type of _generic_arraycopystub_cnt is int and it occupies 32-bit in memory on Linux/RISC-V. That's why we use incrementw here which increments a 32-bit memory operand. Note that incrementl works for 64-bit memory operand. Hope that explains. Thanks.

Is this RISC-V specific postfix naming? On x86, there is `b`/`w`/`l`/`q` for 1/2/4/8-byte ops, respectively. This is just my curiosity, it does not block the integration.

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PR: https://git.openjdk.org/jdk/pull/9461