RFR: JDK-8283865: riscv: Break down -XX:+UseRVB into seperate options for each bitmanip extension

[Fei Yang]

On Wed, 30 Mar 2022 07:02:06 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> Currently openjdk riscv supports RISC-V bitmanip extension as a bundle while spec provides four individual extensions: Zb[abcs][1].
> 
> According to the spec, we need to break down `UseRVB` into two individual options `UseZba` and `UseZbb` to enable or disable Zba and Zbb respectively (openjdk riscv only supports Zba and Zbb for now).
> 
> Since multi-letter extensions representation in the ISA bitmap is still not determined [2][3], availability for those extensions could not be queried from HWCAP. Feature detection of Zba and Zbb was removed temporarily.
> 
>  Linux RISCV64 release hotspot/jdk tier1 tests are  passed on QEMU with following options:
> - [x] +UseZba && +UseZbb
> - [x] +UseZba && -UseZbb
> - [x] -UseZba && +UseZbb
> 
> [1]: https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf
> [2]: http://lists.infradead.org/pipermail/linux-riscv/2021-November/010250.html
> [3]: http://lists.infradead.org/pipermail/linux-riscv/2021-November/010252.html

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1524:

> 1522: // Rd[31:0] = Rs[23:16] Rs[31:24] Rs[7:0] Rs[15:8] (zero-extend to 64 bits)
> 1523: void MacroAssembler::revb_h_w_u(Register Rd, Register Rs, Register tmp1, Register tmp2) {
> 1524:   if (UseZba && UseZbb) {

Requiring availability of both ISA-extensions here might not be a good idea in respect of performance.
We should have more fine-grained distinguishment making use of instructions for each ISA-extension when possible.

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PR: https://git.openjdk.java.net/jdk/pull/8032