RFR: 8288047: Accelerate Poly1305 on x86_64 using AVX512 instructions [v5]

Tue Nov 1 23:34:34 UTC 2022

On Fri, 28 Oct 2022 20:19:35 GMT, vpaprotsk <duke at openjdk.org> wrote:

> And just looking now on uops.info, they seem to have identical timings?

Actual instruction being used (aligned vs unaligned versions) doesn't matter much here, because it's a dynamic property of the address being accessed: misaligned accesses that cross cache line boundary incur a penalty. Since the cache line size is 64 byte in size, every misaligned 512-bit access is penalized.

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PR: https://git.openjdk.org/jdk/pull/10582