RFR: 8295948: Support for Zicbop/prefetch instructions on RISC-V

[Ludovic Henry]

On Wed, 2 Nov 2022 06:11:33 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> The OpenJDK supports generating prefetch instructions on most platforms. RISC-V supports through the Zicbop extension the use of prefetch instructions. We want to make sure we use these instructions whenever they are available.
>> 
>> It passes `hotspot:tier1` test suite
>
> src/hotspot/cpu/riscv/riscv.ad line 5197:
> 
>> 5195:   ins_encode %{
>> 5196:     __ addi(t0, as_Register($mem$$base), $mem$$disp);
>> 5197:     __ andi(t0, t0, ~(CacheLineSize - 1));
> 
> Do we really need to align to CacheLineSize here and in generate_prefetch?
> I didn't see this requirement from the official CMO specification [1]. Could you please confirm that? Thanks.
> 
> [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf

It's indeed not a requirement, let me remove that `andi`.

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PR: https://git.openjdk.org/jdk/pull/10884