RFR: 8295967: RISC-V: Support negVI/negVL instructions for Vector API

[Dingli Zhang]

On Fri, 4 Nov 2022 02:25:11 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> Hi,
>> 
>> This patch will add support of `NegVI`, `NegVL` for RISC-V and was implemented by referring to riscv-v-spec v1.0 [1]. 
>> 
>> Tests are performed on qemu with parameter `-cpu rv64,v=true,vlen=256,vext_spec=v1.0`. By adding the `-XX:+PrintAssembly -Xcomp -XX:-TieredCompilation -XX:+LogCompilation -XX:LogFile=compile.log` parameter when executing the test cases[2] [3] , the compilation log is as follows:
>> 
>> 
>> 100     B16: #	out( B37 B17 ) <- in( B15 )  Freq: 77.0109
>> 100     # castII of R9, #@castII
>> 100     addw  R29, R9, zr	#@convI2L_reg_reg
>> 104     slli  R29, R29, (#2 & 0x3f)	#@lShiftL_reg_imm
>> 108     add R12, R30, R29	# ptr, #@addP_reg_reg
>> 10c     addi  R12, R12, #16	# ptr, #@addP_reg_imm
>> 110     vle V1, [R12]	#@loadV
>> 118     vrsub.vx V1, V1, V1	#@vnegI
>> 120     bgeu  R9, R10, B37	#@cmpU_branch  P=0.000001 C=-1.000000
>> 
>> 
>> At the same time, the following assembly code will be generated: 
>> 
>> 
>>   0x000000400ccfa618:   .4byte	0x10072d7
>>   0x000000400ccfa61c:   .4byte	0xe1040d7                   ;*invokestatic unaryOp {reexecute=0 rethrow=0 return_oop=0}
>>                                                             ; - jdk.incubator.vector.IntVector::lanewiseTemplate at 91 (line 684)
>>                                                             ; - jdk.incubator.vector.Int256Vector::lanewise at 2 (line 273)
>>                                                             ; - jdk.incubator.vector.Int256Vector::lanewise at 2 (line 41)
>>                                                             ; - Int256VectorTests::NEGInt256VectorTests at 73 (line 5216)
>> 
>> 
>> PS: `0x10072d7/0xe1040d7` are the machine code for `vsetvli/vrsub`.
>> 
>> After we implement these nodes, by using `-XX:+UseRVV`, the number of assembly instructions is reduced by about ~50% because of the different execution paths with the number of loops, similar to `AddTest` [4].
>> 
>> In the meantime, I also add an assembly pseudoinstruction `vneg.v` in macroAssembler_riscv.
>> 
>> [1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#111-vector-single-width-integer-add-and-subtract
>> [2] https://github.com/openjdk/jdk/tree/master/test/jdk/jdk/incubator/vector/Int256VectorTests.java
>> [3] https://github.com/openjdk/jdk/tree/master/test/jdk/jdk/incubator/vector/Long256VectorTests.java
>> [4] https://github.com/zifeihan/vector-api-test-rvv/blob/master/vector-api-rvv-performance.md
>> 
>> Please take a look and have some reviews. Thanks a lot.
>> 
>> ## Testing:
>> 
>> - hotspot and jdk tier1 on unmatched board without new failures
>> - test/jdk/jdk/incubator/vector/Int256VectorTests.java with fastdebug on qemu
>> - test/jdk/jdk/incubator/vector/Long256VectorTests.java with fastdebug on qemu
>
> lgtm

@yadongw @RealFYang  Thanks for the review!

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PR: https://git.openjdk.org/jdk/pull/10880