Integrated: 8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

[Dingli Zhang]

On Mon, 7 Nov 2022 01:59:25 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

> Hi,
> 
> At the moment, the operands order of `vrsub_vx` and ` vrsub_vi` is not the same as in the RVV1.0 spec[1]. These instructions use the wrong assembly syntax pattern for vector binary arithmetic instructions (multiply-add)[2].
> 
>  `vrsub_vx` was classified as `Vector Single-Width Integer Add and Subtract` in rvv1.0 spec, but is currently classified as `Vector Single-Width Integer Multiply-Add Instructions` and generate the functions under the corresponding macros, which results in the reverse order of the operands `Vs2` and `Rs1` compared to the spec.
> 
>  `vrsub_vi` has its own separate macro definition to generate the corresponding function and the order of these operands(`Vs2` and `imm`) is reversed too.
> 
> I think it is better to adjust the operands order of these two instructions to be consistent with the spec.
> 
> Please take a look and have some reviews. Thanks a lot.
> 
> 
> [1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
> [2] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#101-vector-arithmetic-instruction-encoding
> 
> ## Testing:
> 
> - hotspot and jdk tier1 on unmatched board without new failures
> - test/jdk/jdk/incubator/vector/Int256VectorTests.java with fastdebug on qemu
> - test/jdk/jdk/incubator/vector/Long256VectorTests.java with fastdebug on qemu

This pull request has now been integrated.

Changeset: 1169dc06
Author:    Dingli Zhang <dzhang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/1169dc066c0257da1a237960b8c0cc4782ef8d14
Stats:     21 lines in 3 files changed: 1 ins; 11 del; 9 mod

8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

Reviewed-by: luhenry, fyang

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PR: https://git.openjdk.org/jdk/pull/11009