RFR: 8296448: RISC-V: Fix temp usages of heapbase register killed by MacroAssembler::en/decode_klass_not_null [v2]

[Xiaolin Zheng]

On Tue, 8 Nov 2022 05:41:21 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix as to comments
>
> src/hotspot/cpu/riscv/riscv.ad line 1741:
> 
>> 1739: 
>> 1740:   Label skip;
>> 1741:   __ cmp_klass(j_rarg0, t1, t0, t2 /* as a tmp */, skip);
> 
> You might also want to add comment for 't0' here: /* as a temp */

The other two are done, and the comments like this are renamed to a friendlier `/* call-clobbered t2 as a tmp */`.

t0 is always used freely as a tmp register, I guess it is not necessary to add a comment for t0? It seems only the newly-added t2 here matters.

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PR: https://git.openjdk.org/jdk/pull/11010