RFR: 8296448: RISC-V: Fix temp usages of heapbase register killed by MacroAssembler::en/decode_klass_not_null [v2]

[Xiaolin Zheng]

On Tue, 8 Nov 2022 14:40:39 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> @zhengxiaolinX Nice catch. Looks good, but I'm not sure that all temporary registers are used safely, especially where non-t0 is used?

Thank you.
I re-examined this patch, and they seem okay to me again.
For the t2 usage in this patch, we may come to the UEP via the `call_stub` when leaving the C++ world, where gcc would help us save alive caller-saved registers. So we can use t2 here. Or, we come to the UEP from the Java world: t2 is SOC so it would have been saved before performing this call if alive.
Some comments in itable stub[1] can also help to make it clear, and in vtable stub[2] it seems we also use a t2 as tmp.
Would this be okay for you :-)?

[1] https://github.com/openjdk/jdk/blob/82cbfb5fb0db61f3f1d9f0ceeed20c1cf5474652/src/hotspot/cpu/riscv/vtableStubs_riscv.cpp#L177-L178
[2] https://github.com/openjdk/jdk/blob/82cbfb5fb0db61f3f1d9f0ceeed20c1cf5474652/src/hotspot/cpu/riscv/vtableStubs_riscv.cpp#L84

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PR: https://git.openjdk.org/jdk/pull/11010