RFR: 8295948: Support for Zicbop/prefetch instructions on RISC-V [v8]

[Fei Yang]

On Wed, 9 Nov 2022 17:02:13 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> The OpenJDK supports generating prefetch instructions on most platforms. RISC-V supports through the Zicbop extension the use of prefetch instructions. We want to make sure we use these instructions whenever they are available.
>> 
>> It passes `hotspot:tier1` test suite
>
> Ludovic Henry has updated the pull request incrementally with one additional commit since the last revision:
> 
>   review

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 1920:

> 1918:   if (is_imm_in_range(imm, 12, 0)) {
> 1919:     and_imm12(Rd, Rn, imm);
> 1920:   } else if (is_power_of_2(~(imm - 1))) {

Since this has been reworked, is this change still necessary then? I assume this won't make a difference in number of instructions emitted as compared with the final else branch?

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PR: https://git.openjdk.org/jdk/pull/10884