RFR: 8295703: RISC-V: Remove implicit noreg temp register arguments in MacroAssembler

[Aleksey Shipilev]

On Thu, 20 Oct 2022 03:12:31 GMT, Fei Yang <fyang at openjdk.org> wrote:

> This is similar to: https://bugs.openjdk.org/browse/JDK-8295257
> 
> Remove implicit `= noreg` temporary register arguments for the three methods that still have them.
>   * `load_heap_oop`
>   * `store_heap_oop`
>   * `load_heap_oop_not_null`
> 
> Only `load_heap_oop` is used with the implicit `= noreg` arguments.
> After [JDK-8293769](https://bugs.openjdk.org/browse/JDK-8293769), the GCs only use explicitly passed in registers. This will also be the case for generational ZGC. Where it currently requires `load_heap_oop` to provide a second temporary register.
> 
> Testing: Tier1 hotspot with fastdebug build on HiFive Unmatched board.

Marked as reviewed by shade (Reviewer).

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PR: https://git.openjdk.org/jdk/pull/10778