RFR: 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V [v11]

[Vladimir Kempik]

On Mon, 24 Oct 2022 12:23:58 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> Thanks for the update. Looks like DEFAULT_CACHE_LINE_SIZE is not defined anywhere? Looks good, otherwise.
>
> It's defined in `src/hotspot/share/utilities/globalDefinitions.hpp` but let me add it in `src/hotspot/cpu/riscv/globalDefinitions_riscv.hpp` just to make sure.

> I overall agree with the 64 bytes is an industry standard. What I want to ensure is that we can eagerly enable `UseBlockZeroing` whenever we can.

I strongly disagree.

Until processor reports Zic64b supported we should assume the cache line size could be anything (2^N). I'm running some tests on risc-v fpga core and it has 16-bytes cache block size.
having to patch ( change default cache line size) and rebuild openjdk to just try new Zicbo{z,p,m} opcodes ( once they are implemented) - isn't a nice way

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PR: https://git.openjdk.org/jdk/pull/10718