RFR: 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V [v16]

[Fei Yang]

On Mon, 24 Oct 2022 13:49:01 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> Similarly to AArch64 DC.ZVA, the RISC-V Zicboz [1] extension provides the cbo.zero [2] instruction that allows to zero out memory a cache-line at a time. This should be faster than storing zeroes 64bits at a time.
>> 
>> [1] https://github.com/riscv/riscv-CMOs
>> [2] https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicboz.adoc#insns-cbo_zero
>
> Ludovic Henry has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix cbo_zero encoding

src/hotspot/cpu/riscv/assembler_riscv.hpp line 2749:

> 2747:   INSN(prefetch_i, 0b0000000000000);
> 2748:   INSN(prefetch_r, 0b0000000000001);
> 2749:   INSN(prefetch_w, 0b0000000000010);

Opcode for prefetch_w is wrong?

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PR: https://git.openjdk.org/jdk/pull/10718