RFR: 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V [v11]

[Ludovic Henry]

On Tue, 25 Oct 2022 08:07:21 GMT, Fei Yang <fyang at openjdk.org> wrote:

>>> I overall agree with the 64 bytes is an industry standard. What I want to ensure is that we can eagerly enable `UseBlockZeroing` whenever we can.
>> 
>> I strongly disagree.
>> 
>> Until processor reports Zic64b supported we should assume the cache line size could be anything (2^N). I'm running some tests on risc-v fpga core and it has 16-bytes cache block size.
>> having to patch ( change default cache line size) and rebuild openjdk to just try new Zicbo{z,p,m} opcodes ( once they are implemented) - isn't a nice way
>
>> > I overall agree with the 64 bytes is an industry standard. What I want to ensure is that we can eagerly enable `UseBlockZeroing` whenever we can.
>> 
>> I strongly disagree.
>> 
>> Until processor reports Zic64b supported we should assume the cache line size could be anything (2^N). I'm running some tests on risc-v fpga core and it has 16-bytes cache block size. having to patch ( change default cache line size) and rebuild openjdk to just try new Zicbo{z,p,m} opcodes ( once they are implemented) - isn't a nice way
> 
> Now I see the concern here. I agree to have the an option for cache-line size in that respect.

I'll revert to what I had to set CacheLineSize then.

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PR: https://git.openjdk.org/jdk/pull/10718