RFR: 8294729: [s390] Implement nmethod entry barriers

[Martin Doerr]

On Wed, 19 Oct 2022 17:17:47 GMT, Tyler Steele <tsteele at openjdk.org> wrote:

>> src/hotspot/cpu/s390/gc/shared/barrierSetNMethod_s390.cpp line 49:
>> 
>>> 47: 
>>> 48:   public:
>>> 49:     static const int BARRIER_TOTAL_LENGTH = GUARD_INSTRUCTION_OFFSET + 2*6 + 2; // bytes
>> 
>> Please either use 14 or something which matches the sequence: 4 (patchable constant) + 6 (larl) + 4 (bcr)
>
> GUARD_INSTRUCTION_OFFSET is the offset to the beginning of the patchable instruction. So, I believe it should be: 6 (cfi) + 6 (larl) + 2 (bcr).
> 
> It may be worth renaming 'GUARD_INSTRUCTION_OFFSET' as I feel it's a bit confusing.

Ok, I thought bcr was 4 bytes. That may be wrong.

>> src/hotspot/cpu/s390/s390.ad line 851:
>> 
>>> 849:   Compile* C = ra_->C;
>>> 850:   C2_MacroAssembler _masm(&cbuf);
>>> 851:   // Register nmethod_tmp = Z_R3;
>> 
>> Don't kill R3! I'd use R0 and R1 only.
>
> I would guess this is because, even though it's a volatile register, R3 can be a parameter or return value. So in the context of the compiler, we really don't want to use this register?
> 
> BTW, I have now removed my changes to this file.

R3 can contain a parameter at this point. You don't want to overwrite it.

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PR: https://git.openjdk.org/jdk/pull/10558