RFR: 8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

[Fei Yang]

Currently G1 (and Shenandoah) implicitly uses x13 in oop_store_at on riscv.

This out of the blue register fixed for x86 in [JDK-8283186](https://bugs.openjdk.org/browse/JDK-8283186).
This would be fixed in the same way on riscv by passing the temporary register explicitly so it is part of the GC API.

Testing: Passed Tier1 test on linux-riscv64 SiFive Unmatched board.

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Commit messages:
 - 8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

Changes: https://git.openjdk.org/jdk/pull/10137/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=10137&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8293290
  Stats: 71 lines in 16 files changed: 2 ins; 0 del; 69 mod
  Patch: https://git.openjdk.org/jdk/pull/10137.diff
  Fetch: git fetch https://git.openjdk.org/jdk pull/10137/head:pull/10137

PR: https://git.openjdk.org/jdk/pull/10137