RFR: 8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

[Fei Yang]

On Fri, 2 Sep 2022 12:47:20 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

>> Currently G1 (and Shenandoah) implicitly uses x13 in oop_store_at on riscv.
>> 
>> This out of the blue register fixed for x86 in [JDK-8283186](https://bugs.openjdk.org/browse/JDK-8283186).
>> This would be fixed in the same way on riscv by passing the temporary register explicitly so it is part of the GC API.
>> 
>> Testing: Passed Tier1 test on linux-riscv64 SiFive Unmatched board.
>
> Looks fine.

@shipilev : Thanks for the review. Also passed Tier2 test. Integrate then.

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PR: https://git.openjdk.org/jdk/pull/10137