RFR: 8293351: Add second tmp register to aarch64 BarrierSetAssembler::load_at [v2]

[Fei Yang]

On Mon, 5 Sep 2022 12:49:14 GMT, Axel Boldt-Christmas <aboldtch at openjdk.org> wrote:

>> Add a second tmp register to the BarrierSetAssembler::load_at GC API for aarch64.
>> 
>> Today G1 and Shenandoah uses a second temporary register. This will also be the case for generational ZGC.
>> 
>> Testing: Oracle platforms tier 1-3
>
> Axel Boldt-Christmas has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Fix argument names

Would you mind a few more tweaks? Thanks.

src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.hpp line 73:

> 71: 
> 72:   void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
> 73:                Register dst, Address src, Register tmp1, Register tmp2);

Need similar modification for function definition in file barrierSetAssembler_aarch64.cpp

src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp line 288:

> 286: 
> 287:   // Is it a weak but alive CLD?
> 288:   __ stp(r10, r11, Address(__ pre(sp, -2 * wordSize)));

No need to save r11 then?

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Changes requested by fyang (Reviewer).

PR: https://git.openjdk.org/jdk/pull/10161