RFR: 8293351: Add second tmp register to aarch64 BarrierSetAssembler::load_at [v2]

[Axel Boldt-Christmas]

On Tue, 6 Sep 2022 03:38:33 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> As `resolve_weak_handle` may call into the VM `r11` may still be clobbered. The reason that `rscratch[1/2]` was not used previously was because  some GC in the `resolve_weak_handle` call graph used them implicitly. This is all explicit now so `rscratch` is used instead as it seems like it is the way the GC API has gone, with all registers being explicit. 
>> 
>> There is still some room for improvement here with regards to being more consistent with what registers are used.
>
> "As resolve_weak_handle may call into the VM r11 may still be clobbered. "
> -- I don't quite understand this.  If this is the case, shouldn't r11 be saved & restored immediate before and after the VM call together with other live caller-save registers?

Maybe? Actually looking at it a second time it seems like r0-r7 and r9-r17 are pushed to the stack at the vm call I was looking at. 
I am probably missing something. I do not fully understand the reason for pushing the registers at this point, not earlier or later. Would have to investigate further. I do however think that such a change belongs to a separate issue/PR. This PR should not change the instruction emission, only which registers are used.

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PR: https://git.openjdk.org/jdk/pull/10161