RFR: 8293351: Add second tmp register to aarch64 BarrierSetAssembler::load_at [v4]

[Stuart Monteith]

On Tue, 6 Sep 2022 06:24:38 GMT, Axel Boldt-Christmas <aboldtch at openjdk.org> wrote:

>> Add a second tmp register to the BarrierSetAssembler::load_at GC API for aarch64.
>> 
>> Today G1 and Shenandoah uses a second temporary register. This will also be the case for generational ZGC.
>> 
>> Testing: Oracle platforms tier 1-3
>
> Axel Boldt-Christmas has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Make tmp register names consistent g1BarrierSetAssembler_aarch64

src/hotspot/cpu/aarch64/gc/g1/g1BarrierSetAssembler_aarch64.cpp line 277:

> 275:                          dst /* pre_val */,
> 276:                          rthread /* thread */,
> 277:                          tmp1 /* tmp */,

For tmp1 and tmp2 the comments, to match the paramter names, would also be "/* tmp1 */" and "/* tmp2 */".

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PR: https://git.openjdk.org/jdk/pull/10161