RFR: 8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at

[Fei Yang]

On Wed, 14 Sep 2022 06:41:25 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

>> This is similar to https://bugs.openjdk.org/browse/JDK-8293351
>> Add a second temporary register for BarrierSetAssembler::load_at GC API on riscv64.
>> Today G1 and Shenandoah uses a second temporary register. This will also be the case for generational ZGC.
>> 
>> Testing: Tier1-3 tested on Linux-riscv64 SiFive Unmatched board.
>
> src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp line 318:
> 
>> 316:     __ push_call_clobbered_registers();
>> 317: 
>> 318:     satb_write_barrier_pre(masm, noreg, dst, xthread, tmp, t0, true, false);
> 
> Is `tmp` not `t0` here? I expected to see `t1` in this diff. Maybe I am missing something.

I don't think 'tmp' is 't0' here since we are asserting they are different registers in ShenandoahBarrierSetAssembler::satb_write_barrier_pre [1]. And I also run non-trivial benchmark work loads like Dacapo, Specjvm and Specjbb using ShenandoahGC with fastdebug build for these changes. 

[1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp#L111

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PR: https://git.openjdk.org/jdk/pull/10261