RFR: 8294087: RISC-V: RVC: Fix a potential alignment issue and add more alignment assertions for the patchable calls/nops [v3]

[Aleksey Shipilev]

On Wed, 21 Sep 2022 10:44:54 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> With RVC turning on, we must carefully keep all runtime-patchable instructions aligned. Code is running at full speed, when patching unaligned instructions spanning cache lines, concurrency issues may occur. This patch fixes a potential alignment issue of the patchable nop after MachUEPNode, with adding some strong alignment assertions as well. (In fact, currently the `nop` in the Verified Entry Point is fortunately aligned to 4 under RVC even without this patch, so this patch doesn't change program behaviors.)
>> 
>> Tested hotspot tier1 and tier2 together with other patches on QEMU.
>
> Xiaolin Zheng has updated the pull request incrementally with one additional commit since the last revision:
> 
>   (Revertible) Just to see which code style is better

I think `static void assert_alignment(address pc, int alignment = NativeInstruction::instruction_size);` is cleaner, even though it requires a new include in `macroAssembler_riscv.hpp`.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 2850:

> 2848: 
> 2849:   address call_pc = pc();
> 2850:   assert(entry.rspec().type() == relocInfo::runtime_call_type || is_aligned(call_pc, 4), "bad alignment for patchable calls");

"4" is still here?

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PR: https://git.openjdk.org/jdk/pull/10370